Semiconductor wafers are typically highly polished with very smooth surfaces (i.e. deviations of less than 1 nm). However, they are not necessarily uniformly flat across the extent of the wafer. The same is true for wafers of ceramic or other materials. Flatness variation, called “wafer bow,” may be a result of the wafer manufacturing process itself or processing of the wafer (e.g. through depositing of metal or dielectric onto the wafer) and can be on the order of 25 μm or more on the concave and/or convex side. If the polished side is concave, the wafer is often referred to as “dished” whereas if it is convex the wafer is called “bowed.” Note however, that an individual wafer can concurrently have both types of non-planarities (i.e. one portion is bowed whereas another portion is dished.
For simplicity herein, the terms “dished,” “bowed” and “non-planar” are interchangeably used herein to generically refer to a non-flat wafer of, for example, semiconductor or ceramic, irrespective of whether it would formally be called dished or bowed. FIG. 1 illustrates, in simplified form, a conventional non-planar wafer 100. As shown, the wafer 100 is between 500 μm and 750 μm thick and has a maximum deviation “δ” at the edges of 25 μm from flat. As a result, in the example of FIG. 1, the deviation from highest to lowest point across both sides is 40 μm. In most cases, with conventional processes for forming chips and interconnecting them to other chips, this amount of bow is sufficiently small relative to the size of typical connections that it can be disregarded. However, such variations can render a wafer unsuitable for use where the pitch and/or height of the individual contacts is less than or equal to 25 μm, unless further expensive polishing operations are performed to reduce the bow to an acceptable level, if it is possible to do so at all. Moreover, if the same types of connections will be used but the chip will be stacked with another chip, the bowing would be on the order of about 50 μm (i.e. taking into account the maximum deviation of 25 μm each for both chips and/or on both sides).
Thus, there is a need for a way to make use of individual wafers that have bow on a side with contacts that are less in height than the bow or on a pitch where such bow could make it impossible to connect to them.